`ifndef _ral_blk_REG_PRJ_sys_irq_rtl_
`define _ral_blk_REG_PRJ_sys_irq_rtl_

`include "vmm_ral_host_itf.sv"

`include "ral_reg_REG_PRJ_sys_irq_global_irq_rtl.sv"


interface ral_blk_REG_PRJ_sys_irq_itf();

logic [0:0] resp_err_out;
logic resp_err_rd, resp_err_wr;
logic [0:0] resp_err_in;
logic resp_err_wen;
logic [0:0] timeout_out;
logic timeout_rd, timeout_wr;
logic [0:0] timeout_in;
logic timeout_wen;
logic [0:0] inner_err_out;
logic inner_err_rd, inner_err_wr;
logic [0:0] inner_err_in;
logic inner_err_wen;


modport regs(output resp_err_out,
             output resp_err_rd,
             output resp_err_wr,
             input resp_err_in,
             input resp_err_wen,
             output timeout_out,
             output timeout_rd,
             output timeout_wr,
             input timeout_in,
             input timeout_wen,
             output inner_err_out,
             output inner_err_rd,
             output inner_err_wr,
             input inner_err_in,
             input inner_err_wen);


modport usr(input resp_err_out,
            input resp_err_rd,
            input resp_err_wr,
            output resp_err_in,
            output resp_err_wen,
            input timeout_out,
            input timeout_rd,
            input timeout_wr,
            output timeout_in,
            output timeout_wen,
            input inner_err_out,
            input inner_err_rd,
            input inner_err_wr,
            output inner_err_in,
            output inner_err_wen);

endinterface



module ral_blk_REG_PRJ_sys_irq_rtl(vmm_ral_host_itf.slave hst,
                                   ral_blk_REG_PRJ_sys_irq_itf.regs usr);
reg hst_ack;
assign hst.ack = hst_ack;
reg [3:0] global_irq_sel;

always @(*)
   begin
      global_irq_sel = 'b0;

      hst_ack = 0;

      if (hst.adr == 'hc) begin
         global_irq_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
   end


wire [31:0] global_irq_out;
ral_reg_REG_PRJ_sys_irq_global_irq_rtl global_irq(hst.clk, hst.rstn,
                                                  hst.wdat[31:0], global_irq_out, global_irq_sel, hst.wen,
                                                  usr.resp_err_out,
                                                  usr.resp_err_rd,
                                                  usr.resp_err_wr,
                                                  usr.resp_err_in,
                                                  usr.resp_err_wen,
                                                  usr.timeout_out,
                                                  usr.timeout_rd,
                                                  usr.timeout_wr,
                                                  usr.timeout_in,
                                                  usr.timeout_wen,
                                                  usr.inner_err_out,
                                                  usr.inner_err_rd,
                                                  usr.inner_err_wr,
                                                  usr.inner_err_in,
                                                  usr.inner_err_wen);


reg [31:0] _rdat;
always @(*)
   begin
      _rdat = 32'b0;
      unique casez ({|global_irq_sel[3:0]})
         1'b1: _rdat = global_irq_out;
         default: _rdat = 32'b0;
      endcase
   end
assign hst.rdat[31:0] = _rdat;

endmodule
`endif
